1. Field of the Invention
The invention relates to an apparatus and method for convolutional interleaving/deinterleaving.
2. Description of the Relevant Art
Present digital communication channels are experiencing greatly increased demands, which lead to errors in the data being transmitted in that channel. The error correcting codes in common use are very good at detecting and correcting isolated bit errors which occur in a communication channel. However, typical error correction and detection codes are insufficient in a channel which is subject to burst-type errors, i.e., errors which will affect a large number of bits of data at a time.
Convolutional interleaving and de-interleaving techniques on either end of the channel transmission path are used to interleave the data stream, so that the effects of burst errors become distributed when the data stream is de-interleaved, and do not overwhelm the error correcting and detecting codes.
A balance often must be maintained among considerations such as, for example, the physical amount of memory used to realize the interleaver/deinterleaver, the total amount of device xe2x80x9creal estatexe2x80x9d available to the device designer, the device performance, device flexibility and dynamic re-programmability, and the simplicity of the device design and implementation. In applications where the importance of spatial efficiency is less important, the interleaver/deinterleaver can be implemented using an arbitrary number of memory cells, provided the requisite device performance characteristics are met. Often, interleavers/deinterleavers are realized using distinct designs and implementations, which can not be reconfigured dynamically to satisfy, for example, the demands of a different environment requiring the use of a different type of interleaver/deinterleaver.
The tension of this balance is most prominent in single-chip signal processing device implementations, where spatial efficiency can become a crucial consideration. There is a need for efficient implementations of certain types of interleavers/deinterleavers, including, for example, a Ramsey Type II device, which to date have not been demonstrated. Furthermore, there is a need for an interleaver/deinterleaver that can be dynamically reconfigurable among the different types of devices, for example, Ramsey I, Ramsey II, Ramsey III, and Ramsey IV.
The invention provides a memory-efficient convolutional interleaver/deinterleaver which includes a memory array, a write commutator, and a read commutator; wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a technique, such as a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver, and a Ramsey Type-III is realized.